According to Abbreviationfinder, SPARC stands for Scalable Processor ARChitecture, which is a RISC big-endian architecture. That is, an architecture with a reduced instruction set.
It was originally designed by Sun Microsystems and directed by engineer Kaa in 1985, it is based on the RISC I and II designs of the University of California at Berkeley that were defined between the years 1980 and 1982. Sun Microsystems company designed this architecture and licensed it to other manufacturers such as Texas Instruments, Cypress Semiconductor, Fujitsu, LSI Logic among others. SPARC is the first open RISC architecture and as such the design specifications are published so other microprocessor manufacturers can develop their own design. One of the innovative ideas of this architecture is the registry window that allows to easily make high-performance compilers and a significant memory reduction in load / store instructions in relation to other RISC architectures. The advantages are especially appreciated in large programs. The SPARC cpu is composed of a whole unit, UI (Integer Unit) that processes the basic execution and a FPU (Floating-Point Unit) that executes the operations and calculations of reals. The UI and the FPU may or may not be built on the same chip. Although not a formal part of the architecture, Sun Microsystems SPARC-based computers have a memory management unit MMU and a large cache of virtual addresses (for instructions and data) that are peripherally arranged on a data and address bus. 32-bit.
- Its distinctive feature is to use registry windows.
- 32 32-bit “integer” registers.
- 16 64-bit floating point registers (for double precision) that can be used as 32 32-bit registers (for single precision).
- Addressing modes:
- Immediate, (13-bit constants).
- Direct, (13-bit offset).
- Indirect, (register + 13-bit offset or register + register).
- Use delayed instructions (jumps, load and store).
- Memory management:
- 4 Gigabyte virtual space.
- MMU memory management unit that works with pages of configurable size.
The SPARC architecture has about 50 integer instructions, a few more than the previous RISC design, but less than half the number of integer instructions in the Motorola 6800. SPARC instructions can be classified into five categories:
- LOAD and STORE (The only way to access memory). These instructions use two registers or a register and a constant to calculate the memory address to address. * Arithmetic / Logical / Shift Instructions. They perform arithmetic, logic, and bit-shifting operations. These instructions calculate the result if it is a 2-operand function and store the result in a register.
- Coprocessor operations. The UI extracts floating point operations from the data bus instructions and queues them for the FPU. The FPU executes the floating point calculations with a fixed number in floating point arithmetic unit, (the number is application dependent). Floating point operations are executed concurrently with UI instructions and with other floating point operations when necessary. The SPARC architecture also specifies an interface for connecting an additional coprocessor. * Transfer Control Instructions. These include jumps, calls, traps, and branches. The transfer control is usually delayed until after the execution of the next instruction, so the pipeline is not flushed because a time control occurs. In this way, compilers can be optimized by lazy branches.
- Read / Write register control instructions. These instructions are included to read and write the contents of various control registers. Usually the source or destination is implicit in the instruction.
A unique feature characterizing the SPARC design is the overlapping register window. The processor has much more than 32 integer registers, but displays 32 at any given time. An analogy can be created by comparing the register window with a rotating wheel. Some part of the wheel is always in contact with the ground; thus when rotating it we take different portions of the wheel, (the effect is similar for the overlap of the registers window). The result of a register is changed to an operand for the next operation, obviating the need for an extra Load and Store instruction. It was agreed for the architecture specification, to be able to have 32 “visible” registers divided into groups of 8.
- From r0 to r7, GLOBAL Registers.
- From r7 to r15, OUTPUT registers.
- From r15 to r23, LOCAL Registers.
- From r24 to r31, INPUT registers.
Global records are “seen” by all windows, locals are only accessible by the current window, and output records overlap with the input records of the next window (output records for a window must be set as output records. entry for the next, and must be in the same record). The window pointer keeps track of which window is currently active. There are instructions to “open” and “close” windows, for example for a “call” instruction, the register window rotates counterclockwise; for the return from a “call” instruction, it is rotated clockwise. An interrupt uses a fresh window, that is, it opens a new window. The number of windows is a parameter of the implementation, usually 7 or 8. The more elaborate alternative to slowly circling the records window is to drop the records at compile time. For languages like C, Pascal, etc., this strategy is difficult and time consuming. Therefore, the compiler is crucial to improve the productivity of the program. “Recent research suggests that the log window, found on SPARC systems but not on other commercial RISC machines, is able to provide excellent performance for development languages such as Lisp and Smalltalk. ” R. Blau, P. Foley, etc. 1984.
Traps and Exceptions
The SPARC design supports a total set of traps or interrupts. They are handled by a table that supports 128 hardware interrupts and 128 software traps. However floating point instructions can be executed concurrently with integer instructions, floating point traps must be exact because the FPU provides (from the table) the addresses of the failing instructions.
Some SPARC instructions are privileged and can only be executed while the processor is in supervisor mode. These instructions executed in protected mode ensure that user programs are not accidentally altered by the state of the machine with respect to its peripherals and vice versa. The SPARC design also provides memory protection, which is essential for multitasking operations. The SPARC has many similarities to the Berkeley design, the RISC II. Similar to RISC II, it uses a register window to reduce the number of Load and Store statements. SPARC according to Sun Microsystems Until recently, RISC architectures performed poorly with respect to floating point calculations. For example, the IBM 801 implemented floating point operations in software. The Berkeley projects, RISC I and RISC II, left out a VAX 11/780 in integer calculations but NOT in floating point arithmetic. This is also true for the Stanford processor, the MIPS. SPARC systems, on the other hand, are designed for optimal performance in floating point calculations and support single, double and extended precision in operands and operations as specified by ANSI / IEEE standard 754 of the floating point standard. The high performance in floating point calculations results from the concurrency of the UI and the FPU. The UI (Integer Unit) does the “load” and “store” while the FPU (Floating Point Unit) executes the operations and calculations. SPARC systems achieve high speeds as a result of improved chip manufacturing techniques. The SPARC system delivers very high levels of performance. The flexibility of the architecture makes future systems capable of much better times than the initial implementation.
- Second generation released in 1992.
- Clock frequencies from 33 to 50 Mhz.
- Super scalar design
ULTRA SPARC II
- Released in mid-1996.
- Super scalar 4-stage 64-bit architecture.
- Five floating point units.
- Speeds between 250 and 300 Mhz.
Advanced Product Line (APL)
- Released mid 2004.
- Business Agreement between Sun Microsystems and Fujitsu
- Super scalar architecture compatible with SPARC V9 64-bit design.
- Speeds between 1.35 and 2.7 GHz.
- Used by Sun Microsystems, Cray Research, Fujitsu / ICL, and others.